As the integration of semiconductor devices advances, three dimensional construction of individual elements to be formed in an active area has become necessary, and, due to this, as the height of elements from the surface of a substrate increase and differences between the heights of elements become more and more severe, planarization of elements using an insulation layer becomes essential for interconnection between the elements.
The planarization, however, causes differences of depths between the contact holes provided for wiring individual elements having different heights from the surface of the substrate. For example, there are differences of depths, such as between a gate strapping contact of a transistor and a contact of a source or drain region, or between a buried bit line contact and a contact of a source or drain region.
Such a difference of depths between contact holes may cause non-uniform contact filling with a selective chemical deposition of metallic material.
That is, as illustrated in FIG. 1, when contact holes are formed for exposing surfaces of designated conduction lines, such as, gate 2 and impurity diffusion region 3 of a transistor formed on substrate 1, a difference of depths of contact holes formed in layer 4 is caused by the difference of heights of gate 2 and impurity diffusion region 3 from the surface of substrate 1. In case such contact holes having different heights are buried with metallic material 5, such as tungsten, the burying may not be complete in the deeper contact hole, while the burying in the lower contact hole may be excessive.
In case of burying a metal into contact holes having various contact depths with a selective deposition of metal, the maximum depositable thickness of the metal is restricted by the depth of the contact hole having the lowest depth. Reference is made to R. J. Saia, et al., Tungsten and Other Refractory Metals for VLSI Application III. edited by V. L. Wells (MRS, Pittsburgh, Pa.) pp. 349, 1987. Therefore, even though the lowest contact hole may be buried fully, the deepest hole may not be buried fully, which makes the metal wiring process difficult.
Due to this, a method that uses a chemical deposition of polycrystal silicon has been suggested as a method for fully burying contact holes having different depths existing in one element at the same time. Reference is made to K. K. Choi, et al., Proc. VLSI Multilevel Interconnection Conf., pp. 286, 1992.
The method for fully burying contact holes of different depths using chemical deposition of polycrystal silicon is illustrated in FIG. 2A. After forming contact holes exposing designated conduction lines, for example, bit line 6 and impurity diffusion region 3 formed on substrate 1 through planarized insulation layer 4 (in this example, the difference of depths of the contact holes is caused by the difference of heights of bit line 6 and impurity diffusion region 3 from the surface of substrate 1), polycrystal silicon 7a is deposited over the insulation layer including the contact holes.
As illustrated in FIG. 2B, after carrying out an anisotropic dry etching of deposited polycrystal silicon 7a, polycrystal silicon layers 7b remain only on the side walls of the contact holes. By carrying out a selective deposition of tungsten 5 thereon, tungsten is grown at the bottoms and sides of the contact holes, and the contact holes can be buried irrespective of the depths of the contact holes.
Since deposition of polycrystal silicon and anisotropic etching of the deposited polycrystal silicon must be carried out, however, the method has problems, such as requiring complicated processes and damaging the conduction layers under the bottoms of the contact holes as a consequence of the etching.